InhaltsangabeAbout the Author xvii Preface xix Acknowledgments xxiii 1 Analog, ESD, and EOS 1 1.1 ESD in Analog Design 1 1.2 Analog Design Discipline and ESD Circuit Techniques 2 1.3 Design Symmetry and ESD 5 1.4 ESD Design Synthesis and Architecture Flow 6 1.5 ESD Design and Noise 7 1.6 ESD Design Concepts: Adjacency 8 1.7 Electrical Overstress 8 1.8 Reliability Technology Scaling and the Reliability Bathtub Curve 13 1.9 Safe Operating Area 15 1.10 Closing Comments and Summary 17 References 18 2 Analog Design Layout 19 2.1 Analog Design Layout Revisited 19 2.2 Common Centroid Design 22 2.3 Interdigitation Design 24 2.4 Common Centroid and Interdigitation Design 24 2.5 Passive Element Design 25 2.6 Resistor Element Design 25 2.7 Capacitor Element Design 29 2.8 Inductor Element Design 30 2.9 Diode Design 33 2.10 MOSFET Design 35 2.11 Bipolar Transistor Design 36 2.12 Closing Comments and Summary 36 References 37 3 Analog Design Circuits 39 3.1 Analog Circuits 39 3.2 SingleEnded Receivers 40 3.3 Differential Receivers 41 3.4 Comparators 43 3.5 Current Sources 43 3.6 Current Mirrors 44 3.7 Voltage Regulators 46 3.8 Voltage Reference Circuits 49 3.9 Converters 49 3.10 Oscillators 50 3.11 Phase Lock Loop 50 3.12 Delay Locked Loop 50 3.13 Closing Comments and Summary 52 References 52 4 Analog ESD Circuits 55 4.1 Analog ESD Devices and Circuits 55 4.2 ESD Diodes 55 4.3 ESD MOSFET Circuits 59 4.4 ESD Silicon-Controlled Rectifier Circuits 62 4.5 Laterally Diffused MOS Circuits 64 4.6 DeMOS Circuits 68 4.7 Ultrahigh-Voltage LDMOS Circuits 69 4.8 Closing Comments and Summary 72 References 72 5 Analog and ESD Design Synthesis 73 5.1 Early ESD Failures in Analog Design 73 5.2 MixedVoltage Interface: Voltage Regulator Failures 73 5.3 Separation of Analog Power from Digital Power AVDD to DVDD 76 5.4 ESD Failure in Phase Lock Loop (PLL) and System Clock 77 5.5 ESD Failure in Current Mirrors 77 5.6 ESD Failure in Schmitt Trigger Receivers 78 5.7 Isolated Digital and Analog Domains 82 5.8 ESD Protection Solution: Connectivity of AVDD to VDD 82 5.9 Connectivity of AVSS to DVSS 83 5.10 Digital and Analog Domain with ESD Power Clamps 84 5.11 Digital and Analog Domain with Master/Slave ESD Power Clamps 86 5.12 HighVoltage, Digital, and Analog Domain Floor Plan 87 5.13 Closing Comments and Summary 88 References 88 6 AnalogtoDigital ESD Design Synthesis 89 6.1 Digital and Analog 89 6.2 Interdomain Signal Line ESD Failures 90 6.3 DigitaltoAnalog Core Spatial Isolation 92 6.4 DigitaltoAnalog Core Ground Coupling 92 6.5 DomaintoDomain Signal Line ESD Networks 94 6.6 DomaintoDomain ThirdParty Coupling Networks 94 6.7 DomaintoDomain CrossDomain ESD Power Clamp 95 6.8 DigitaltoAnalog Domain Moat 96 6.9 DigitaltoAnalog Domain Moat with ThroughSilicon Via 96 6.10 DomaintoDomain ESD Design Rule Check and Verification Methods 97 6.11 Closing Comments and Summary 97 References 97 7 AnalogESD Signal Pin Cosynthesis 101 7.1 Analog Signal Pin 101 7.2 Analog Signal Differential Receiver 102 7.3 Analog CMOS Differential Receiver 108 7.4 Analog Differential Pair ESD Signal Pin Matching with Common Well Layout 110 7.5 Analog Differential Pair Common Centroid Design Layout: Signal Pin-to-Signal Pin and Parasitic ESD Elements 113 7.6 Closing Comments and Summary 115 References 116 8 Analog and ESD Circuit Integration 119 8.1 Analog and Power Technology and ESD Circuit Integration 119 8.2 ESD Input Circuits 120 8.3 Analog ESD Output Circuits 123 8.4 Analog ESD Ground-to-Ground Networks 124 8.5 ESD Power Clamps 125 8.6 ESD Power Clamps for Low-Voltage Digital and Analog Domain 129 8.7 ESD Power Clamp Issues 137 8.8 ESD Power Clamp Design 138 8.9 Bipolar ESD Power Clam

Hersteller:
Wiley-VCH GmbH
product_safety@wiley.com
Boschstr. 12
DE 69469 Weinheim

Steven H. Voldman, IEEE Fellow, Vermont, USA

Leseprobe